The present invention relates to a process of fabricating a semiconductor integrated circuit device and, more particularly, to a technique effective when applied to a semiconductor integrated circuit device which has a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal, i.e., a refractory metal layer or a silicide layer made of a compound of a refractory metal and silicon.
In order to realize a high-speed operation, one of the important subject matters of a folded bit line type DRAM (i.e., Dynamic Random Access Memory) is to reduce the resistance of a word line. It is, therefore, conceivable to use as the word line a conductive layer which is prepared by covering a polycrystalline silicon layer with a silicide layer composed of a refractory metal and silicon. The silicide layer is featured in that it has a lower resistance than the polycrystalline silicon layer and in that it is remarkably stable for the atmosphere at the various treating steps of the fabricating process like the polycrystalline silicon layer. This polycrystalline silicon layer bears abundant fruit when used in the semiconductor technique and has such a high reliability that a refractory metal in the silicide layer can be prevented from affecting the electrical characteristics of the semiconductor integrated circuit device.
In DRAM, a MISFET acting as a switching element of a memory cell frequently has its gate electrode integrated with the word line at an identical fabrication step. There is disclosed in Japanese Patent Laid-Open No. 57-194567 the concept that the polycrystalline silicon layer is formed beneath the silicide layer so that the threshold voltage of the MISFET may not fluctuate.